Condensed Matter Seminar Series

M.F. Gonzalez-Zalba

Hitachi Cambridge Laboratory, Cambridge, UK

Gate-based Readout: Optimization and Scaling

In the quest for scaling up silicon-based quantum computing, readout by already existing gate electrodes has gained prominence due to its reduced impact in the qubit layout and comparable sensitivities to conventional charge sensors. Gate-based sensing enables readout of spins by projective measurements using the state-dependent differential capacitance of the system [1]. Recently, single-shot readout has been achieved with this technique [2-4] but further improvements are necessary to set gate-based readout well above quantum error-correction thresholds.

In this talk, I will present results that highlight the steps to optimize gate-based readout. At the device level, the dispersive signal can be enhanced by increasing the gate-coupling to the quantum system using for example high-k dielectrics and 3D thin SOI technology [5]. At the resonator level, a high loaded quality factor and good matching to the line are essential. These can be achieved by using superconducting elements and optimal circuit topologies [6]. Ultimately, at the electronics level, the sensitivity could be further improved by reducing the noise floor using quantum-limited Josephson parametric amplification.

Last, I will explain how gate-based readout can be combined with digital technology to read multiple quantum devices sequentially while reducing the number of resonators to facilitate scaling. I will show results on digitally-interfaced dynamic readout of transistor-based silicon quantum devices [7].


[1]  R. Mizuta, et al. Phys. B. 95 045414 (2017)
[2]  A. West, et al. Nat Nano (2019)
[3]  P. Pakkiam, et al. PRX 8 041032 (2018)
[4]  G. Zheng et al., arXiv:1901.00687 (2019)
[5]  M. F. Gonzalez-Zalba, et al. Nat. Commun. 6 6084 (2015)
[6]  I. Ahmed, et al.  Phys. Rev. App.  10, 014018 (2018).
[7]  Schaal et al. Phys Rev App 9 054016 and Nat Elect (2019).